As performance speeds of integrated circuits (ICs) continue to increase, the ability to test such high-speed devices becomes more difficult. In particular, high-speed ICs are very challenging to test because very often the high-speed IC is capable of operating faster than the testing device. One of the solutions to overcome such testing device limitations is to build a frequency multiplier on-chip. Conventionally, this has been performed by fabricating a complicated, on-chip phase-locked loop (PLL) circuit. However, such a solution adds both complexity and cost to the fabrication process.